1. Field of the Invention
The present invention relates generally to large VLSI circuit designs and more particularly to computer-aided timing analysis of sequential circuits.
2. Background Art
CMOS Technology has made massive strides over the last two decades and is now the dominant choice for large VLSI designs. Recent projections on changes in technology have shown that great changes are required in design methodologies of the future to keep pace. Specifically, due to increases in design complexity, it will be essential for designers to place an even greater reliance on computer-aided design (CAD) tools to ensure the required increase in productivity. With timing optimization becoming one of the all-important factors as clock frequencies are forced upwards, CAD strategies for timing optimization are becoming essential. Traditional techniques that consider one combinational block at a time in a sequential circuit can no longer suffice, and more aggressive sequential timing optimization will be required.
A general sequential circuit is a network of computation nodes (gates) and memory elements (registers). The computational nodes may be conceptualized as being clustered together in a network of gates that forms a combinational logic circuit.
Pipelined systems are a special subset of the class of general sequential circuits, and are primarily used in datapaths. A pipelined system uses registers to capture the output of each logic stage at the end of each clock period. Data proceeds through each combinational block, or pipeline stage, until it reaches the end of the pipeline, with the registers serving to isolate individual stages so that they may parallel process data corresponding to different data sets. The use of this parallelism causes an increase in the data throughput rate of the system.
Physically a Netlist is a set of interconnected components. A high level Netlist can be above the component level. A Netlist is a method for going from some level of conceptual design to component design. The most structured Netlist is a layout of physical components and their interconnections which can go to a manufacturer who can actually make the chip from that most sophisticated and complicated Netlist. There are two categories of components, the pure combinational component and the sequential component. Combinational components consist of AND gates, OR gates and the like. Combinational components have outputs which change depending on the input. In sequential components, the output does not necessarily depend on the data inputs, but changes only after a clock input or enable input is also received, making these sequential components synchronous devices.
The period of the clock signal should be longer than the total delay between two sequential components through one or more combinational components so that when a clock signal triggers the output to follow the input, the data at the input is already there and appropriate for that particular input. The data has to be there when the clock signal arrives, otherwise it isn""t good data. If the total delay through the combinational components is greater than the clock period, then the design will not work. What the designer wants to do before sending the design to the manufacturer, is to use a timing verifier to verify that everywhere in the design, every arc of delay through a series of combinational components is smaller than the clock period. The timing verifier receives a Netlist. It also receives a component library which has a series of look-up tables which tell the timing verifier what is the delay of each component in the Netlist. The timing verifier reads in the Netlist, gets the timing information for each component from the library and then propagates the timing and checks to see if it is proper. The timing verifier also recognizes sequential elements from the library. The timing verifier also receives the clock period information. Each region between two sequential components has to be checked by the time verifier individually to see if it satisfies the clock period criteria. If there is a problem in timing where the arc delay does not satisfy the clock period criteria, the user has two choices. He can either modify the clock period or change the design. The timing verifier is a software tool which issues informational reports which report either that all the timing is proper or identifies those combinational logic regions where the timing is a problem. The Netlist is provided as an ASCI file. It also generates a timing data structure which records so much information that its memory has to be greater than the Netlist data structure and the bigger the design, the more time it will take for the timing verifier to verify that all of the timing constraints are satisfied. The average chip can be huge, having dozens of millions of components. Therefore, most chip designs employ a divide and conquer methodology where the chip is divided into a large number of interior blocks and each one is assigned to a different designer. One design architect will have the responsibility of putting all the blocks together to form the entire chip. If one were to verify the timing of an entire design, the required memory may be more than the analysis memory available and in addition the CPU time for the verifier would be so long as to be unacceptable.
Another timing analysis software tool is called the timing budgeter. The timing budgeter is designed to assess the placement criticality regarding timing delays between blocks. The timing budgeter uses the same information as the timing verifier and the data Netlist and it is entirely dependent upon the timing verifier algorithm in terms of determining where the critical timing delays are located between blocks.